Director of Engineering – ML Hardware Design & Architecture

Stack

Responsibilities

• ▹Architect high-performance, power-efficient ML hardware accelerator designs, especially for computer vision workloads (image classification, object detection, video analytics)
• ▹Analyze and optimize hardware for performance, power and area (PPA) tradeoffs
• ▹Define hardware micro-architecture for efficient implementation of ML algorithms
• ▹Lead HW IP development, working closely with RTL design, verification, synthesis and physical design teams
• ▹Collaborate closely with global hardware, software and systems teams
• ▹Work with cross-functional teams (HW design, verification, SW, systems, marketing, product planning) to align architecture with product goals
• ▹Use models, simulators, profilers and real hardware to justify architectural decisions quantitatively
• ▹Apply knowledge of CPUs, GPUs, DSPs, memory and bandwidth analysis to ML hardware design
• ▹Communicate results and technical issues effectively with leads and peers
• ▹Invent and file patents for innovative hardware solutions

Requirements

• ▹Experience in hardware development for ML, multimedia or accelerator technologies (vision, imaging, video, display, audio)
• ▹Experience in system or chipset development for SoC products, preferably in the mobile market
• ▹Familiarity with OS principles and HW/SW interaction
• ▹Experience with SoC bus, interconnect and memory technologies
• ▹MS degree with 15+ years of industry experience: architecture/micro-architecture of ML or multimedia cores, ML frameworks (TensorFlow Lite, ONNX), VLSI design and verification (Verilog/SystemVerilog/HLS), C/C++/SystemC programming, simulators and performance/power models, scripting and automation
• ▹Bachelor's degree in Computer or Electrical Engineering, Computer Science, or related field and 8+ years of Software/Hardware/Systems Engineering experience (or Master's + 7 years, or PhD + 6 years)

Nice to have

• ▹Deep domain knowledge in ML for vision (image/video processing, neural network architectures for vision)
• ▹Experience collaborating with global teams across multiple time zones and cultures
• ▹Experience working with synthesis and physical design teams for HW IP development and PPA improvement
• ▹Excellent communication, documentation and presentation skills
• ▹Demonstrated technical and people leadership

Soft skills

What we offer

• ▹Pay range: $228,400-$342,600
• ▹Annual discretionary bonus program
• ▹Opportunity for annual RSU grants
• ▹Competitive benefits package