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Staff/Sr. Staff RTL Design Engineer – QGOV

Other • Principal • On-site • Full-time United States San Diego, USA

A digital design engineering role based in San Diego (5 days/week on-site) covering micro-architecture design, RTL development, debugging, and post-silicon bring-up support for complex digital blocks.

Responsibilities

  • Design micro-architecture for simple and complex digital and interface blocks
  • Develop RTL code following industry best practices, handling multi-clock designs, high-frequency requirements, low power and low latency
  • Troubleshoot and debug issues, support post-silicon bring-up activities
  • Create comprehensive design documentation
  • Optimize designs for area, power and performance
  • Collaborate with cross-functional teams (DFT, Implementation, Verification, Emulation, Firmware)

Requirements

  • Must be in San Diego full time, 5 days a week
  • 6-10+ years of experience with RTL/FPGA design (Verilog, SystemVerilog), embedded system architecture and verification
  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field and 5+ years of Hardware Engineering experience (or Master's + 5 years, or PhD)
  • Minimum: Bachelor's + 6 years / Master's + 5 years / PhD + 4 years of ASIC design, verification, validation or integration experience

Nice to have

  • Positive attitude and team spirit
  • 5+ years of ASIC design experience
  • RTL expertise: SystemVerilog design, linting, CDC, synthesis (FPGA and ASIC)
  • Building test suites for design validation
  • Understanding of emulation and prototyping flows for lab design and validation
  • Experience designing complex digital logic blocks and subsystems (CPU, GPU, DSP, always-on systems, digital interfaces: PCIe, UART, I2C, DDRx, SPI, USB)
  • Familiarity with ISAs such as ARM THUMB or RISC-V
  • Understanding of processor or microcontroller system design
  • Experience with multi-power-domain and multi-clock-domain designs
  • Proficiency in scripting/automation languages like Python or Perl
  • Familiarity with industry-standard digital design tools
  • Awareness of challenges with lower node technologies

Soft skills

Positive attitudeTeamworkProblem solvingCollaborating with diverse teams

What we offer

  • Pay range: $164,000-$246,000
  • Annual discretionary bonus program
  • Opportunity for annual RSU grants
  • Competitive benefits package
Education: BSc+6 év / MS+5 év / PhD+4 év ASIC-tervezési tapasztalat, számítástechnika, villamos-/elektronikamérnöki vagy kapcsolódó területen.

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