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3D Memory Chip Architect and Design, Principal Engineer

Software Architect • Principal • On-site • Full-time United States San Diego, USA

Qualcomm's Custom Memory Team, part of the Process & Package Solutions Group, is seeking a role focused on 3D memory design and architecture for memory-centric compute systems (data center, mobile, compute, XR), improving bandwidth, latency, power, thermal and area efficiency.

Responsibilities

  • Develop and optimize 3D DRAM/FLASH organization and near-memory computing architectures for high density, high TOPS/mm2 and high TOPS/W
  • Develop and validate models for 3D memory performance, power and yield as a function of bank, TSV and power distribution choices
  • Develop novel fabrics for robust distribution of high-bandwidth data from 3D DRAM memory arrays to near-memory computing units across mobile, compute and XR workloads
  • Develop power distribution topology enabling robust memory operation in the 3D stack
  • Simulate and emulate system performance of 3D memory architecture choices across AI, compute and mobile workloads
  • Floorplan 3D memory chips and design memory array control structures under 3D integration manufacturing constraints, testability, repairability and performance requirements
  • Apply knowledge of chip connection fabrics such as UCIe, UAL, LPDDR, HBM3/4 and PCIe

Requirements

  • Bachelor's degree in Science or Engineering and 8+ years of ASIC design, verification, validation or integration experience (or Master's + 7 years, or PhD + 6 years)

Nice to have

  • Experience in RTL, circuit and system design to model and optimize dataflow
  • Experience in SoC architecture and power/clock/bus design
  • Experience in DRAM/FLASH architecture performance assessment
  • Experience in memory circuit design (SRAM/DRAM/FLASH/ROM etc.)
  • Experience in a programming language (C/C++/Python) or scripting language (Perl/Python)
  • Ability to develop Verilog/Verilog-A/Verilog-AMS models of critical dataflow
  • Familiarity with DRAM/FLASH datasheets and IO interfaces
  • Experience in ASIC design, mixed-signal design and performance modeling
  • Good knowledge of memory architecture, buses and 2.5D/3D integration
  • Proficiency in EDA tools, MATLAB and Python
  • Master's or PhD in Electrical Engineering, Computer Science or related field

Soft skills

Self-starter with good communication and team spiritStrong problem-solving and analytical skillsAbility to work independently and as part of a team

What we offer

  • Pay range: $192,000-$288,000
  • Annual discretionary bonus program
  • Opportunity for annual RSU grants
  • Competitive benefits package

About the company

Qualcomm's Custom Memory Team, part of the Process & Package Solutions Group, works on 3D memory architecture and design for memory-centric compute systems across data center, mobile, compute and XR applications.

Education: BSc+8 év / MS+7 év / PhD+6 év ASIC-tervezési tapasztalat, természettudományi vagy mérnöki területen; MS/PhD villamosmérnöki vagy számítástechnika terület előny.

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