RTL Design Engineer

Stack

Responsibilities

• ▹Write and own synthesizable RTL in SystemVerilog across blocks from datapath logic to control and memory interfaces
• ▹Author functional verification environments using UVM, cocotb, formal property checking, or a combination
• ▹Work with architecture to translate high-level specifications into implementable microarchitectures
• ▹Collaborate with physical design on timing closure, floorplanning constraints, and DFT
• ▹Develop and maintain simulation infrastructure, regression pipelines, and coverage closure flows
• ▹Participate in design reviews and contribute to architecture decisions, not just implementation
• ▹Support tapeout preparation, integration, and post-silicon bring-up as needed

Requirements

• ▹Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route
• ▹Experience authoring verification environments in UVM, cocotb, formal, or equivalent
• ▹At least one tapeout in your background, from any node and any company size
• ▹Comfort operating across both design and verification without treating them as separate disciplines
• ▹Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
• ▹Strong debugging instincts across simulation, waveforms, and formal counterexamples
• ▹Ability to work directly with architects and physical designers without needing a large intermediary layer
• ▹Industry experience in ASIC or SoC design

Nice to have

• ▹Experience at an AI chip company where design and verification were tightly coupled
• ▹Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6
• ▹Familiarity with RISC-V or other open ISAs
• ▹Experience with AI-assisted RTL or EDA tooling in your design workflow
• ▹Exposure to physical design constraints, floorplanning, or timing-driven RTL development

Soft skills

About the company

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource — stochastic, in-memory, asynchronous architectures that deliver 10-100x more AI inference per dollar and per watt. The company co-designs the full stack, from AI-native EDA systems used by the world's largest semiconductor companies to the advanced ASICs they make possible. Backed by $85M+ from leading deep-tech investors, the team works across New York, Silicon Valley, London, Copenhagen, and Seoul.