
About the role Own verification of our AI compute core - tensor pipelines, MAC arrays, accumulator logic, and the compute ↔ memory interconnect. Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out. What you'll do Own verification of our AI compute core - tensor pipelines, MAC arrays, accumulator logic, and the compute ↔ memory interconnect Use and develop AI-assisted tool flows to accelerate datapath verification timelines What we're looking for 5+ years of experience verifying compute-heavy blocks (CPU (floating point), GPU, NPU, DSP, or AI accelerator) Abilities in arithmetic and datapath verification (tensor pipelines, MAC arrays, FP / INT accumulators) Proficient in C++, SystemVerilog, UVM, and Python Hands-on with verification methodology - constrained-random verification, coverage-driven closure, and debug across long pipelines Preferred qualifications Strong understanding of numerical correctness (FP rounding, denormals, saturation) and golden-model comparison Familiarity with formal methods (FPV, DPV), writing custom golden models in C++ or Python Familiarity with a commercial formal tool like JasperGold or VC_Formal Compensation Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO. Visa Sponsorship DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status. Export Controls Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview. Equal Opportunity DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request. Full compensation packages are based on candidate experience and relevant certifications. California pay range $180,000 — $275,000 USD Compensation Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO. Visa Sponsorship DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status. Export Controls Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview. Equal Opportunity DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
Hasonló állások
Állás
Digital Verification Engineer
Efficient Computer
CppVerilog
💰 Bér: nincs megadva
🏢 Helyszíni
San Francisco
🗣️ EN

Állás
ASICS Design Verification Engineer
Qualcomm
CppVerilogVhdl
101 400–152 200 USD/év
bruttó
🏢 Helyszíni
San Diego
🗣️ EN

Állás
ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems
Qualcomm
CppVerilog
101 400–152 200 USD/év
bruttó
🏢 Helyszíni
San Diego
🗣️ EN
Állás
Microarchitect and RTL Designer - Compute
MatX
CppHaskellVerilog
💰 Bér: nincs megadva
🌍 Remote
Mountain View (HQ) or Remote
🗣️ EN

Állás
GPU Power Engineer
Qualcomm
CppVerilog
141 300–211 900 USD/év
bruttó
🏢 Helyszíni
San Diego
🗣️ EN

Állás
Next-Gen System Cache ASIC Digital Design Engineer
Qualcomm
CppVerilog
121 800–182 600 USD/év
bruttó
🏢 Helyszíni
San Diego
🗣️ EN