Host and Network IO FPGA Engineer

Stack

Responsibilities

• ▹Lead full chassis-to-wafer IO architecture and design
• ▹Improve current RTL, implement next-gen FPGA design, define future IO architectures
• ▹Produce production-ready bitstreams for deployment into large clusters
• ▹Work with the DV team to prevent bug slips and simplify debug
• ▹Optimize bandwidth and latency across the FPGA datapath and IO interfaces
• ▹Work with the board team on board bringup
• ▹Drive network performance debug of large AI clusters
• ▹Integrate leading-edge networking technologies and protocols
• ▹Lead cross-functional technical projects spanning multiple teams

Requirements

• ▹5+ years of industry experience producing production FPGA solutions, OR Master's/PhD in Computer or Electrical Engineering plus 3 years industry experience
• ▹Proficiency in Verilog development in a Git-based repo
• ▹Strong proficiency in FPGA placement & routing, timing closure, simulation, debug and related FPGA tooling
• ▹Familiarity with network protocols (TCP, RoCE) and network debug tools such as Wireshark
• ▹Knowledge of network switch environments or willingness to learn (Arista, Juniper, etc.)
• ▹Use of AI-augmented development tools

Soft skills

About the company

Cerebras builds the world's largest AI chip, 56 times larger than a GPU, delivering industry-leading training and inference speed; its partners include leading model labs, large enterprises and OpenAI.