Principal Engineer - CAD, SoC Floorplan and Advanced Technode

Stack

Responsibilities

• ▹Develop advanced SoC floor-planning methodologies for complex hierarchical and multi-die designs
• ▹Define and optimize power delivery network (PDN) implementation for advanced-node designs, including IR/EM-aware planning
• ▹Build scalable automation and methodologies for floor-planning, power mesh, clocking, IO/IP integration and routing congestion analysis
• ▹Drive methodology innovations for advanced technology nodes, ultra-low voltage designs, and chiplet/multi-die systems
• ▹Collaborate with leading foundries and EDA partners on future implementation strategies

Requirements

• ▹Strong expertise in SoC design flow automation, hierarchical floor-planning and PDN design
• ▹Solid programming and scripting skills, including Python, C, EDA tools, and version control systems (Git)
• ▹Hands-on experience with low-power design methodologies, UPF-based design, chip finishing and physical verification flows in advanced process technologies
• ▹Excellent problem-solving, communication and collaboration skills across globally distributed teams
• ▹Proven ability to lead technical initiatives with internal engineering teams, foundries and ecosystem partners

Nice to have

• ▹Deep understanding of advanced clocking structures, power delivery optimization and physical verification convergence techniques
• ▹Familiarity with AI-assisted design automation and methodology optimization flows

Soft skills

What we offer

• ▹Work at the forefront of advanced SoC and multi-die system design
• ▹Collaboration with leading foundries and EDA partners
• ▹Competitive salary

About the company

The employer is a semiconductor design company at the forefront of advanced SoC and multi-die system design, working in close partnership with leading foundries and EDA software vendors.