System Performance Modeling Engineer

Stack

Responsibilities

• ▹Participate in NoC topology and system memory architecture exploration campaigns with key architects
• ▹Analyze complex datasets to define requirements for next-generation SoCs
• ▹Drive architecture-oriented performance and power explorations across platform-level components (NoC, memory subsystem, system cache, memory controllers)
• ▹Develop new tools for architecture validation and exploration, focused on performance and power modeling
• ▹Support exploratory methodology projects involving machine learning and data science
• ▹Expand, maintain and document innovative modeling frameworks

Requirements

• ▹Robust understanding of computer architecture, memory hierarchy and system/platform architecture
• ▹Experience or knowledge in NoC architecture, topologies and design trade-offs
• ▹Strong knowledge of Object-Oriented Programming (C++, Python)
• ▹Knowledge of bus components and interconnect micro-architecture
• ▹Understanding of performance/power/area trade-offs
• ▹Degree in Microelectronics, Computer Science, or related field
• ▹Preferably 2–5 years of solid experience in SoC modeling and/or software development; strong new graduates considered
• ▹Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite and NoC concepts and topologies
• ▹Experience in Data Science, Machine Learning

Nice to have

• ▹Master's or PhD degree in Microelectronics, Computer Science, or related field
• ▹Strong mathematical background
• ▹Knowledge of NoC architecture and network traffic engineering
• ▹Knowledge of Memory Controller, LPDDR & DDR protocols
• ▹Experience driving architecture-oriented performance/power investigations on NoC, memory controller, system cache, CPU, GPU, multimedia

Soft skills

What we offer

• ▹Annual discretionary bonus program
• ▹Opportunity for annual RSU grants
• ▹Highly competitive benefits package
• ▹Indicative pay range: $115,600–$173,400

About the company

Qualcomm Technologies, Inc.'s Infrastructure IP Team designs platform infrastructure hardware components (interconnect, system cache, memory controllers, System MMU) implemented across all Qualcomm SoCs.