← Zurück zur Liste

Stelle
DSP - FEC Design Engineer
Sonstige
• Vor Ort
• Vollzeit
•
Ottawa, Kanada
About the Role: Celero Communications Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. We are looking for skilled and motivated engineers to join our team and help us build optical transceivers for next-generation optical modems. The ideal candidate must have a strong theoretical background in coding theory, digital communications, and error correction techniques, with experience developing high-performance forward error correction (FEC) algorithms for high-speed communication systems. Candidates with industry experience are preferred. Locations : Ottawa, Ontario, Canada and Vancouver, British Columbia, Canada Key Responsibilities Research, develop, and evaluate forward error correction (FEC) schemes for high-speed optical communication systems. Design and optimize soft-decision FEC algorithms suitable for high-throughput optical modem implementations. Develop and evaluate coding schemes such as LDPC, staircase codes, or related high-performance FEC architectures. Model and simulate FEC performance in optical communication systems, including interaction with DSP blocks and channel impairments. Analyze performance trade-offs including coding gain, latency, throughput, and implementation complexity. Develop floating-point and fixed-point simulation models for algorithm verification. Implement bit-accurate and cycle-accurate models supporting ASIC implementation. Collaborate closely with DSP, ASIC, firmware, and verification teams to ensure efficient hardware implementation. Document algorithm design and simulation results. Preferred Qualifications Master’s or Ph.D. degree in Electrical Engineering, Mathematics, Computer Engineering, or related field. Strong background in coding theory and error correction algorithms. Experience with FEC schemes for communication systems, particularly soft-decision FEC. Familiarity with LDPC, staircase codes, product codes, or related modern FEC techniques. Experience evaluating coding gain, BER performance, and decoder complexity. Programming experience in C/C++, Python, MATLAB, or similar languages. Experience in modeling communication systems. Familiarity with DSP algorithms for communication systems. Experience with version control systems, specifically GitHub. Familiarity with hardware implementation considerations and languages such as Verilog or VHDL is a plus. Team player with a mindset focused on the successful delivery of the first product. Why Join Us The chance to play a foundational role at a high-growth semiconductor start-up. Work on cutting-edge optical communication technologies powering AI and hyperscale data centers. A collaborative, international team culture where ideas and initiative are valued. The opportunity to grow alongside Celero as we scale and shape the future of our industry. Salary Range $150,000 - $250,000 Base Annually The final offer will be determined based on job-related skills, experience, qualifications, and location.
Ähnliche Stellen

Stelle
Optical DSP Design Engineer
Celero Communications, Inc.
CppVerilog
+1
134 385–223 975 €/Jahr
brutto
🏢 Vor Ort
Ottawa
🗣️ EN

Stelle
Experienced Radar Signal Processing Engineer (SAR)
Ubiq Aerospace
CppVerilogVhdl
💰 Gehalt: keine Angabe
🏢 Vor Ort
Trondheim
🗣️ EN

Stelle
ASICS Design Verification Engineer (Vancouver, Markham OR Remote)
Qualcomm
CppVerilogVhdl
96 757–141 553 €/Jahr
brutto
🌍 Remote
Vancouver
🗣️ EN

Stelle
Pre-Award: MXM- Computer Engineer IV
Barbaricum
Cpp
+6
💰 Gehalt: keine Angabe
🏢 Vor Ort
Crane
🗣️ EN

Stelle
FPGA Engineer - Electronic Warfare
Harmattan Ai
SimulinkVerilogVhdl
💰 Gehalt: keine Angabe
🏢 Vor Ort
Paris
🗣️ EN

Stelle
ASICS Design Verification Engineer
Qualcomm
CppVerilogVhdl
90 844–136 356 €/Jahr
brutto
🏢 Vor Ort
San Diego
🗣️ EN