Design Verification Engineer

Stack

Responsibilities

• ▹Review AI-generated collateral to help shape product strategy in collaboration with the ML team
• ▹Provide design verification for internal hardware projects
• ▹Set up and evaluate EDA tools, ensuring internal tool usability and effective deployment
• ▹Develop testbench environments, assertions, and coverage from design documents
• ▹Curate and annotate datasets linking chip specifications to specific test cases
• ▹Establish rigorous quality criteria for verification data
• ▹Implement data augmentation methods and automated quality assurance checks
• ▹Generate synthetic data using AI-based methods
• ▹Collaborate with ML teams to ensure synthetic data effectively challenges verification models
• ▹Build automated pipelines to annotate test data and link it to chip specifications
• ▹Automate document parsing (datasheets, protocol specifications) for contextual tagging and traceability

Requirements

• ▹5+ years of experience in digital verification at a major semiconductor or EDA tool company
• ▹Advanced proficiency in SystemVerilog and UVM methodology
• ▹Experience with EDA verification tools (vManager, Xcelium, Jasper)
• ▹Proficiency in Python or Perl scripting
• ▹Proven expertise in end-to-end design verification: test plan creation, stimulus generation, feature extraction
• ▹Excellent written and spoken communication skills

Soft skills

About the company

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource: instead of forcing determinism onto physics, its stochastic, in-memory, asynchronous chips deliver 10-100x more AI inference per dollar and watt. The team works as one across New York, Silicon Valley, London, Copenhagen, and Seoul, backed by $85M+ from leading deep-tech investors.