Astera Labs

110 offene Stellen 7 Länder 1% Remote 💸 Gehälter · ~5.4M Ft

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Wo rekrutiert wird

USA 68

Israel 26

Taiwan 7

Indien 4

Kanada 2

Deutschland 2

Singapur 1

San Jose · 52Tel Aviv-Yafo, Tel Aviv District, Israel · 19San Jose, California, United States · 13Taipei, Taiwan · 6Bengaluru, Karnataka, India · 4Haifa District · 2California · 2Research Triangle Park · 1

Tech-Stack

69 Cpp 24 Verilog 22 AI/ML 19 17 16 14 9 5 4 3 Labview 3 Llm 3 2 2 2

+3 weitere Technologien

2 1 SQL 1

📋 Gemischte Aktualität

✓ 100% frisch bestätigt (≤3 Tage) (110 aktive Anzeigen)
•Median-Alter der Anzeigen: 46 Tage

Aus den Anzeigendaten, basierend auf unserer täglichen Prüfung. Keine Angabe des Unternehmens und keine Bewertung.

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Astera Labs

Offene Stellen

Principal Signal and Power Integrity Engineer

Principal Engineering Program Manager (EPM)

STA Physical Design Engineer, Senior Principal

Firmware Engineer Tech Lead

Senior ATE Test Engineer

Principal Design Verification Engineer- SerDes/PHY IP

Manager, ATE Test Engineering

Principal Design Verification Engineer

Lead Emulation Engineer

Product Technical Chip Lead, Senior Director

Senior Principal Engineer - Field Applications

Technical Lead Package Platform Engineer

Firmware/Software Tech Lead

Principal Photonics Packaging Architect

Regional Principal Product Application Engineer (Asia)

PCIe Post-Silicon Validation Engineer

Principal Product Applications Engineer

PCIe Post-Silicon Validation Engineer

Sr. Principal Silicon Applications Engineer, AI Infrastructure

Principal Product Applications Engineer, Custom Silicon

Tech Lead Design Engineer

Principal Software Integration Engineer

Director Engineering Operations

Principal Product Application Engineer

Optical Validation Engineer, Principal

Principal Physical Design Engineer

Senior Principal Engineer PD

Principal Analog Mixed-Signal Design Engineer

Tech Lead Design Engineer

Principal Optical Assembly Engineer

Advanced Package Engineer, Principal

Senior Principal ASIC Design Engineer

Distinguished ASIC Design Engineer

Senior Principal Engineer, Security Architect (2026- 346)

Senior Principal Engineer, Offensive Security (2026-345)

Principal SerDes Bring-up Validation Engineer (2026-376)

Optical / Photonics Validation Engineering, Senior Director

Fabric Modeling and Analysis Engineer for Scale Up Fabric (2026-325)

Physical Design Engineering, VP

Performance Engineer

Tech Lead Physical Design Engineer, Power Integrity

Principal Physical Design Engineer, Methodology

Technical Lead Power Engineer

Technical Lead Physical Design Engineer

Technical Chief of Staff for ASIC Engineering

Staff/ Principal Physical Design STA Engineer

Staff/ Principal Physical Design Engineer - SoC EMIR Expert

Staff/ Principal Physical Design CAD Engineer

Staff/ Principal Design Verification Engineer

Staff/ Principal Chip Top Physical Design Engineer

Staff / Principal ASIC Design Engineer

Staff Physical Design Engineer - SoC EMIR Engineer

Staff DFT Engineer

Sr. Principal Program Manager, ASIC Post-Silicon Engineering

Sr. Principal Business Manager – Data Center & AI Infrastructure

Silicon Technical Program Manager

Senior/Tech Lead Silicon Validation Engineer

Senior/Staff System Validation Engineer

Senior/ Staff Physical Design Engineer

Senior/ Staff Package Design Engineer