Astera Labs

122 offene Stellen 9 Länder 💸 Gehälter · ~5.6M Ft

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USA 63

Israel 24

Indien 10

Taiwan 8

Singapur 6

Kanada 5

Deutschland 3

China 2

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San Jose · 31 San Jose, California, United States · 30 Tel Aviv-Yafo, Tel Aviv District, Israel · 16 Bengaluru, Karnataka, India · 8 Taipei, Taiwan · 7 Toronto, Ontario, Canada · 5 Ahmedabad, Gujarat, India · 2 Haifa District, Israel · 2

Tech-Stack

81 Verilog 33 Cpp 25 25 13 AI/ML 10 9 4 4 3 Labview 3 Llm 3 2 1 Azure Devops 1 1

+5 weitere Technologien

1 1 1 Powershell 1 SQL 1

📋 Gemischte Aktualität

✓ 100% frisch bestätigt (≤3 Tage) (122 aktive Anzeigen)
•Median-Alter der Anzeigen: 64 Tage

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Astera Labs

Offene Stellen

Principal Post-Silicon Validation Engineer

Firmware Engineer

Director ASIC Technical Program Management

Principal Digital Design Engineer

Tech Lead Analog Mixed-Signal IC Layout Engineer

Teach Lead Physical Design Engineer

Senior Analog Mixed-Signal IC Layout Engineer

Principal Physical Design Engineer

Analog Mixed Signal Design Engineer

Senior Manager, Global Safety & Security

Principal Physical Design Engineer

Principal Mixed Analog Design Engineer

Principal Physical Design CAD Engineer

Principal Product Applications Engineer

Senior Firmware SW Engineer

Principal SerDes Bring-up Validation Engineer

Principal FW/SW Engineer

Senior Principal Test Engineer

Tech Lead, Digital Design Engineer

Principal Product Technical Leader — AEC/SCM

Principal Logic Design Engineer

Principal Engineer - Validation Engineering

Principal Verification Engineer

Tech Lead Engineer, Design Verification

Tech Lead, Digital Design Engineer

Senior Digital Design Engineer

Senior Design Verification Engineer

Principal Analog Mixed-Signal Design Engineer

AE| Principal Product Application Engineer (Scorpio)

Principal Analog Mixed-Signal Design Engineer

Principal Field Applications Engineer

Silicon Digital IP / Subsystem Architect

Principal Product Applications Engineer

DFT Engineer

Principal Logic Design Engineer - UALink IP/Subsystem

Lead Logic Design - PCIE IP/Subsystem Engineer

Senior System Validation Engineer

Principal/ Sr.Principal Digital Design Engineer

Principal/ Sr Principal Digital Design Engineer

Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet

Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet

Principal Digital Design Engineer

Principal Digital Design Engineer

Senior STA Engineer

Senior Design Verification Engineer

Principal Analog Mixed-Signal Design Engineer

Test Engineer

Senior Digital Design Engineer

Lead Logic Design for UALink IP/Subsystem Engineer

Principal Emulation Engineer

Principal Engineering Program Manager (EPM)

STA Physical Design Engineer, Senior Principal

Firmware Engineer Tech Lead

Senior ATE Test Engineer

Principal Design Verification Engineer- SerDes/PHY IP

Principal Design Verification Engineer

Product Technical Chip Lead, Senior Director

Senior Principal Engineer - Field Applications

Regional Principal Product Application Engineer (Asia)

PCIe Post-Silicon Validation Engineer